Three-dimensional 4F<sup>2</sup> ReRAM cell with CMOS logic compatible process

Abstract

A new three dimensional vertical bipolar junction transistor (BJT) ReRAM cell with CMOS compatible process is reported. A new logic compatible BJT is vertically formed underneath the resistive stacked film of TiN/Ti/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN as a high performance current driver and bit-cell selector. Using a shallow and tiny NLDD to be an emitter connects with ReRAM film as the bitline, a very thin and self-aligned P-pocket implant to be the wordline, and the N-well is the collector of cells. As a result, the new 3D vertical ReRAM cell is very area-saving and efficiently operated by the high gain (β>;50) BJT with a low voltage of 2V for reset and 1.5V for set. By adapting the highly shrinkable 3D BJT current driver in ReRAM, the cell is decoupled with gate length and oxide thickness of logic MOSFETs so that it can be easily scaled down to 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by the lithographic limitation of defining ReRAM film with F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.