15nm-W<inf>FIN</inf> high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

Abstract

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INV</inf> -normalized G <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M,SAT,INT</inf> of 6.7 nm.mS/µm, the Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</inf> Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</inf> / sGe pFinFETs presented in this work improve the performance by ∲90% as compared to the state-of-the-art relaxed-Ge FinFETs.