J-Springs - innovative compliant interconnects for next-generation packaging

Abstract

The advances made in the design and the fabrication of integrated circuits (ICs) have far outpaced the advances made in the design and the fabrication of chip-to-substrate interconnects as well as high-density substrates. According to the International Technology Roadmap for Semiconductors (ITRS) for 2014, the chip-to-substrate interconnects should have a pitch of about 40 /spl mu/m and should be able to accommodate the coefficient of thermal expansion (CTE) mismatch of low-cost organic substrates without resorting to expensive reliability solutions. In this paper, a novel chip-to-substrate interconnect - J-Spring - is proposed and fabricated. J-Spring is a compliant interconnect fabricated through stress-engineered metal layers, and the fabrication is based on traditional IC fabrication process. The J-Springs have excellent compliance in the three orthogonal directions, and the interconnect is designed to accommodate the high differential displacement due to CTE mismatch between silicon ICs and organic substrates under various thermal conditions.