Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs

Abstract

High permittivity (K) gate insulators are projected for sub-100 nm Si MOSFETs since direct tunneling will likely limit SiO/sub 2/ thicknesses to 1.0-1.5 nm. High-K insulators avoid tunneling, but their larger physical thicknesses introduce subtle capacitive coupling phenomena such as fringing-induced barrier lowering (FIBL) that can compromise off-state leakage. In this study, device simulation examines both on and off-state drain current with very high-K gate insulators and sidewall spacers to reveal new source-side and boundary condition effects. Asymmetric devices help to distinguish the effects. A study of stacked gate insulators demonstrates a 10% increase in drive current achieved with high-K spacers in 50 nm devices.