Impact of grain number fluctuations in the MOS transistor gate on matching performance

Abstract

This paper presents a compact model for the gate impact on MOS transistor matching. It is based on the random variations of grain number in the polycrystalline gate. The model is validated by fitting mismatch increase with substrate bias. This study highlights the importance of local polysilicon depletion and gives a better understanding of complex mechanisms that are responsible for MOSFET mismatch.