Backend dielectric etch induced wafer arcing mechanism and solution

Abstract

A significant challenge for dielectric etching in advanced chip designs is a new plasma damage phenomenon called "wafer arcing." This randomly occurring problem is characterized by burned metal and "worm-like" arcing marks along the wafer's edge and the conducting wide metal lines around the die periphery. Arcing-induced particles also increase chamber contamination, requiring more maintenance and downtime. With the impact on yield per wafer, minimizing the frequency has become a key selection criterion for dielectric etch systems, especially for 300 mm manufacturing. Wafer arcing is a response to particular wafer surface structure conditions and plasma instability. Most conducive to this problem are dielectric etch process steps with a prior conductive layer beneath, such as pad and via etch. Arcing can be significantly reduced by a combination of cathode design to support better plasma stability, and electrostatic chuck and process kit design to minimize field gradients across the wafer. In addition, equipment operation parameter settings and process recipes can be optimized to reduce wafer arcing frequency. Providing an advanced chamber design has enabled us to achieve superior wafer arcing performance of less than 1 in 20,000 wafers.