Substrate network modeling for CMOS RF circuit simulation

Abstract

The effect of the substrate network models for use in small-signal CMOS RF circuit simulation is examined in conjunction with the BSIM3 MOSFET model. Detailed comparisons of the small-signal Y and S parameters have been done with both two-dimensional device simulations and measurement data. These comparisons have been made for different bias conditions and channel lengths. It is shown that a simple, one resistance, substrate network model is accurate for small-signal analyses up to a frequency of 10 GHz in a 0.5 /spl mu/m CMOS process.