Publication | Closed Access
Topology-related upset mechanisms in design hardened storage cells
21
Citations
9
References
2002
Year
Unknown Venue
Hardware SecurityDefect ToleranceElectrical EngineeringTopology-related Upset MechanismsEngineeringSeu HardnessLatch RedundancyHardware ReliabilityApplied PhysicsComputer ArchitectureComputer EngineeringSemiconductor MemoryLaser ExcitationElectronic PackagingMicroelectronicsBeyond Cmos
The SEU hardness of a new CMOS storage cell based on latch redundancy has been analyzed using a laser beam simulation. We detected and investigated topology-dependent upset mechanisms due to charge collection at two sensitive nodes using a laser excitation between the nodes. Compact upset-immune device topologies are proposed, using spacing and isolation techniques for simultaneously sensitive node pairs, to achieve high immunity levels required in critical applications.
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