High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process

Abstract

Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder.