Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture

Abstract

The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded debugger based the JTAG boundary scan architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for testability problems. We designed the RED (reusable embedded debugger) using the JTAG boundary scan architecture. The proposed debugger is applicable for not only chip test but also software debugging. Our debugger has an additional hardware module (EICEM: embedded ICE module) for more critical real-time debugging.