2002 · 11 citations · 7 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware Description LanguagesLow-power DesignHigh-level SynthesisLogic SynthesisLow-power Digital Circuit DesignPower OptimizationAsynchronous Circuit DesignAsynchronous Digital Circuit DesignAsynchronous Sequential CircuitsLogic DecompositionLogic GatesLow-power SynthesisPower ConsumptionVhdl
The approach relies on normalcy conditions for STG behavioural specification, ensuring implementability in monotonic and negative gates, and is positioned against other speed‑independent synthesis methods. The paper proposes an approach to synthesize asynchronous speed‑independent circuits using monotonic logic gates and introduces techniques for refining STG specifications into implementable forms. The method employs an ASIC gate array library (IBM SA‑12E) and refines STG specifications to produce implementable monotonic logic circuits. Compared to the Petrify CAD tool, the approach eliminates the need for negligible‑delay inverters while avoiding glitches, and experimental results show 28 % area and 23 % power savings versus non‑monotonic logic decomposition, especially for complex specifications, at the cost of a 6 % speed reduction.
An approach to synthesis of asynchronous speed-independent circuits in monotonic logic gates (e.g. ASIC gate array library IBM SA-12E) is discussed. It is based on the normalcy conditions for STG behavioural specification, which guarantees implementability in monotonic and negative gates. The paper presents techniques for refining the STG specification to an implementable form. It is crucial that in comparison with other speed-independent synthesis methods, e.g. those in the Petrify CAD tool, this approach does not require the use of inverters with negligible delays in order to guarantee the absence of glitches or hazards in the circuits. Experiments with STG benchmarks, involving our new refinement techniques and VHDL simulation, indicate an average reduction of 28% in area and 23% in power consumption against solutions based on non-monotonic logic decomposition. These savings are more noticeable for more complex STG specifications. Such gains are however paid by an average of 6% decrease in circuit speed.
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Kees van Berkel · Integration · 1992 · 160 citations
Dynamic logic in four-phase micropipelines
Steve Furber, J. Liu · 2002 · 63 citations
Engineering, Computer Engineering, Electrical Engineering +17
Monotone Functions in Sequential Circuits
Gyula Magó · IEEE Transactions on Computers · 1973 · 33 citations