Ga 2 O 3 ( Gd 2 O 3 ) ∕ Si 3 N 4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion

Abstract

A dual-layer gate dielectric approach for application in III-V metal-oxide-semiconductor field-effect transistor (MOSFET) was studied by using ultrahigh vacuum deposited 7–8nm thick Ga2O3(Gd2O3) as the initial dielectric to unpin the surface Fermi level of In0.18Ga0.82As and then molecular-atomic deposition of ∼2–3nm thick Si3N4 as a second dielectric protecting Ga2O3(Gd2O3). The total equivalent oxide thickness achieved in this study is 5nm. We have demonstrated an enhancement mode In0.18Ga0.82As∕GaAs MOSFET with surface inverted n channel with drain current (Id) of 0.1mA for a gate length of 10μm and a gate width of 880μm at Vds=1V and Vg=4.5V.