An improved pass-gate adiabatic logic

Abstract

Presents an improved pass-gate adiabatic charge-recovery logic (IPGL) which is efficient in power consumption and requires only moderate reversibility overhead. The energy efficiency is achieved by completely eliminating non-adiabatic loss during the charge phase of the clock, and the reversibility overhead is kept low by allowing partial reversibility only at nodes with small capacitance. We also show how to implement flip-flops with adiabatic logic and propose an adiabatic binary counter. The power dissipation comparison shows, that the IPGL outperforms previous adiabatic logic families, and it dissipates less energy than its static CMOS counterpart for operating frequencies below 400 MHz.