European Solid-State Circuits Conference · 1998 · 23 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignLow-power Digital Circuit DesignTiming AnalysisTiming ModelingCmos Logic CircuitsDetector DesignDigital Logic CircuitsLow-power Design For TestabilityLow-power Electronics InterfaceLow-power Logic DesignMinimum DistanceWinner-take-all Circuits
This paper describes a minimum-distance detector based on a time-domain technique. In this technique, Hamming-distance of data is translated to delay time, and the minimum distance one fastest data is selected using a time-domain winner-take-all circuit. We describe that this technique is possible to realize using simple logic circuits so that it can achieve small chip area and short delay time. We fabricated test chips for the detector, and demonstrated 21.6[ns] for detecting the minimum distance data from eight 16-bit data, using 1.2µm CMOS technology. We show a data encoding chip for low power chip interface as an application of the detector.
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Sub-1-V swing bus architecture for future low-power ULSIs
Y. Nakagome, K. Itoh, M. Isoda et al. · 2003 · 29 citations
Engineering, Computer Engineering, Electrical Engineering +17