On-chip multi-GHz clocking with transmission lines

Abstract

In the production of high-speed LSIs, clocking becomes a performance limiter when the clock frequency increases to one gigahertz and beyond. The major obstacles to the reduction of clock-skew are: (1) clock-skew sensitivity to variations in device parameters, supply voltages, and temperatures, (2) inductive effects, which are complicated by the resistance reduction needed for faster signal transmission in such networks as grid or fish-bone clocking networks and (3) power consumption. Taking advantage of the effect of inductance and using a 100 mm/sup 2/ 5 GHz clocking network overcomes these obstacles. The network is notable for (1) 20 ps pp clock skew due to a clock tree/grid structure that takes light speed into consideration, (2) controllability of characteristic impedance due to a multilayered and patterned ground plane microstrip structure, (3) high immunity to process and power supply variations due to use of impedance-controlled transmission line effects, and (4) 66% power reduction due to reflected wave recycling.