Clocking design and analysis for a 600 MHz Alpha microprocessor

Abstract

The clocking methodology for the 600 MHz Alpha microprocessor allows increased performance goals to be met through multi-level buffering. In addition power savings are realized through reduced metal usage and conditional clocks. Two distinct analysis methods are required to verify the clock design. One is used for large, globally distributed clocks and the other is applied to small, locally distributed clocks. The clock is generated from an 80-200 MHz reference clock multiplied by an on-chip phase-locked loop (PLL) to a nominal frequency of 600 MHz. The clock distribution network up to and including the global clock (GCLK) is included in the feedback loop of the PLL to control phase alignment. GCLK is the primary timing reference for the chip. The generation of GCLK begins at the PLL and is routed through a high-gain buffer network to a central point on the die. From there the clock is driven through buffered X, H and RC trees to distributed GCLK drivers located in a windowpane pattern across the chip. The final physical stage of the global clock distribution network is a grid of upper-level low-impedance metal that covers the entire die.