2015 · 218 citations · 37 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault ToleranceFault-tolerant ComputingCache Behavior AnalysisMemory Hierarchy DesignMemory Hierarchy OptimizationMemory ModelingMemory Subsystem DesignArchitecture ModelsArchitecture-level OptimizationCache Memory ModelingCache Performance ModelingData Cache BehaviorExecutable Architecture ModelsMemory Refresh TechniquesRetention Time Correction
Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention times of cells, and perform faster refresh only for a few rows which have cells with low retention times. Unfortunately, retention times of some cells can change at runtime due to Variable Retention Time (VRT), which makes it impractical to reliably deploy multirate refresh. Based on experimental data from 24 DRAM chips, we develop architecture-level models for analyzing the impact of VRT. We show that simply relying on ECC DIMMs to correct VRT failures is unusable as it causes a data error once every few months. We propose AVATAR, a VRT-aware multirate refresh scheme that adaptively changes the refresh rate for different rows at runtime based on current VRT failures. AVATAR provides a time to failure in the regime of several tens of years while reducing refresh operations by 62%-72%.
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An experimental study of data retention behavior in modern DRAM devices
Jamie Liu, Ben Jaiyen, Yoongu Kim et al. · 2013 · 287 citations