Prashant J. Nair - Concepedia

Author

Prashant J. Nair

Also Known As

Jaleel, Aamer, Nair, Prashant J., Nair, Prashant Jayaprakash; Roberts, David A., Prashant J Nair, Prashant J. Nair, Prashant Jayaprakash Nair, Prashant Nair, Prashant R. Nair

Publications

2.2K

Citations

H-Index

Concepts

All Affiliations

Georgia Institute of Technology University of British Columbia American Rock Mechanics Association Kyungpook National University Carnegie Mellon University

About

Prashant J. Nair is an author at Georgia Institute of Technology specializing in engineering, computer science, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	26	30	2K
2	Computer Engineering	25	29	2K
3	Computer Science	25	29	2K
4	Management	1	1	29
5	Natural Sciences	1	1	50

Prashant J. Nair

Publications

2.1K

Citations

H-Index

Page 1

	Year	Citations
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems Moinuddin K. Qureshi, Dae-Hyun Kim, Samira Khan, Hardware SecurityNon-volatile MemoryMemory ArchitectureEngineeringEdge Computing	2015	218
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Hardware SecurityNew Dram DesignArray ComputingEngineeringEdge Computing	2016	218
ArchShield Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi Hardware SecurityFuture Dram DevicesElectrical EngineeringDevice VariationEngineering	2013	161
Architectural Support for Mitigating Row Hammering in DRAM Memories Dae-Hyun Kim, Prashant J. Nair, Moinuddin K. Qureshi IEEE Computer Architecture Letters Hardware SecurityEngineeringData ScienceEdge ComputingHigh-performance Architecture	2014	142
DEUCE Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi Hardware SecurityNon-volatile MemoryData Encryption StandardEngineeringEncrypted Storage	2015	113
A Case for Multi-Programming Quantum Computers Poulami Das, Swamit Tannu, Prashant J. Nair, EngineeringQuantum System SoftwareQuantum AlgorithmsComputer ArchitectureQuantum Programming Languages	2019	111
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Multiple Memory AccessesEngineeringComputer ArchitectureMemory Model (Programming)Formal Verification	2018	91
A case for Refresh Pausing in DRAM memory systems Prashant J. Nair, Chiachen Chou, Moinuddin K. Qureshi Non-volatile MemoryEngineeringRefresh PausingLatency PenaltyRefresh Operations	2013	89
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, EngineeringInformation SecurityComputer ArchitectureConfidential ComputingSoftware Analysis	2018	81
Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows Gururaj Saileshwar, Bolin Wang, Moinuddin K. Qureshi, EngineeringInformation SecurityComputer ArchitectureSide-channel AttackVictim Rows	2022	64

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