A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 μm CMOS technologies and beyond

Abstract

Shallow trench isolation schemes using a LOCOS edge to avoid sharp corner effects are applied to 0.25 /spl mu/m and 0.18 /spl mu/m technologies. Two variations are studied. In the first case (Case A) a mini-LOCOS is grown and deglazed prior to trench etch whereas in the second case (Case B) the deglaze is omitted. Excellent narrow width effect is demonstrated. The V/sub T/ increases by /spl les/50 mV when the transistor width is reduced from 10 /spl mu/m to 0.3 /spl mu/m. Minimum isolation space of 0.3 /spl mu/m and minimum n/sup +/-to-p/sup +/ space of 0.6 /spl mu/m across a well boundary are demonstrated. Diode leakages and oxide reliability are reasonable. Transistor subthreshold characteristics show no double hump for Case A, while for Case B some devices indicate presence of double hump when a substrate back bias is applied. Despite the mini-LOCOS formation the width reductions are /spl les/0.05 /spl mu/m and excellent drive currents of 660 /spl mu/A//spl mu/m (NMOS) and 290 /spl mu/A//spl mu/m (PMOS) are achieved corresponding to I/sub off/=1 nA//spl mu/m and V/sub cc/=1.8 V.