Scaling beyond the 65 nm node with FinFET-DGCMOS

Abstract

Exponential growth in leakage power density with physical scaling is driving ULSI technology towards innovative device architectures. Double-gate CMOS (DGCMOS), achieved through use of the Delta Device (D.Hisamoto et al, IEDM 1989, p.833-836), or FinFET (X.Huang et al, IEDM 1999, p.67-70), provides both a tactical solution to the gate-leakage challenge and a strategic scaling advantage. FinFET fabrication is very close to that of the conventional CMOS process, with only minor disruptions, yielding the potential for a rapid deployment to manufacturing. Planar circuit designs have been converted to FinFET-DGCMOS without disruption to physical area.