Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks

Y.H. Kim

2005 · 23 citations · 0 references

Concepts

Abstract

We present a systematic examination of work function modulation and scavenging effect on fully silicided gates using different NiSi alloys (Ti, Hf, Zr, Pd, Pt, and Al) as well as different phases (Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sub> Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sub> and Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rich</sub> -Pt-Si). It is shown that the interface layer between gate FUSI and dielectric is the key to modulate the work function. FUSI alloys were able to prevent Fermi level pining on HfSiO and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> by modification of the top interface. A ~400 meV work function shift was achieved toward the conduction band edge using NiAlSi demonstrating a mobility of 300 cm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Vs at peak, matching NiSi control devices on Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x </sub> SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> . Interface engineering with FUSI alloy gate has not only shown threshold voltage modulation but also enabled further gate oxide scaling (0.15 ~ 0.2nm) compared to NiSi control device. Additional gate oxide scaling is due to the increase of effective dielectric constant in the FUSI gate stack. TEM, EELS, and EDX showed that work function modulation is attributed to the Al pile up at interface. Ni rich silicide FUSI gates showed a ~250mV shift from mid gap toward valence band edge with elimination of Fermi-level pining by modification of the top dielectric interface