A comparative study of switching activity reduction techniques for design of low-power multipliers

Abstract

The design of portable battery-operated systems requires multiplication circuits of low switching activity. This paper studies multiplication algorithms, sign extension methods, adding structures, resource sharing and component schematic alternatives from the point of decreasing the total number of logic transitions in the target multiplication circuit. Experiments show, that by utilizing the signed-digit encoding scheme, modified sign extension technique, 4-2 adding compressors and swing restored transistor path logic, a twice as low switching activity can be achieved.