Thin oxide reliability

Abstract

Dielectric breakdown and oxide and interface charge trapping set the scaling limits for thin oxides. Oxide leakage is far from being the limit. Dielectric breakdown is modeled by hole trapping at "weak" sites with local, above-average current density or large hole trap density. This model predicts a linear relationship between in t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf> and 1/F rather than E. It provides a framework for predicting oxide reliability as a function of area and stress condition from limited data. Using this model and the field experience of thin-oxide EEPROM, it is estimated that 0.01% failure per thousand hour is achievable with 9.5 nm oxides at 5V. This is adequate for 1M-bit DRAMs. Charge trapping and interface trap generation sets slightly less restrictive limit for gate oxides. "Defect" reduction holds promise for improving oxide reliability. New dielectrics will probably be necessary at 4M-bit level unless 10 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> capacitors are available or cell operation is changed. 6.5 nm oxide should be acceptable for 3.3V operation. Again EEPROMs will provide the real-life test for production thin oxide at that thickness.