A BiCMOS logic gate with positive feedback

Abstract

It is noted that, as BiCMOS process technology is refined, the supply voltage must be reduced due to the lower endurance voltage of the devices and the larger power dissipation of the LSI chips. As the MOS drain current decreases with supply voltage, the base current from the MOS in a BiCMOS logic gate should then be sufficient for high-speed switching. Also, as the threshold voltage of the MOS becomes lower, a full logic swing function is necessary, even for BiCMOS gates, to ensure that a DC current does not flow in the next gate. These problems were solved with a BiCMOS logic gate with positive feedback, which was fabricated using a 0.5- mu m BiCMOS device and applied to a channelless gate array for a high-speed processor. Characteristics of the proposed logic gates are summarized. Experimental t/sub pd/ and P/sub d/ versus C/sub L/ characteristics for the three-input NAND at 4-V supply voltage are shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>