Design of vedic multiplier using adiabatic logic

Abstract

A multiplier is a vital element in many arithmetic and logical units, digital signal processing and communication system. Therefore speed, area and power consumptions are the critical parameters for the designing of multiplier circuits. This paper presents a comparative study of binary Vedic multiplier using CMOS, PFAL and ECRL. The design is based on ancient Indian Vedic mathematics and the low power charge recovery logic. In Vedic multiplication, generation of partial sums and products is performed in single step so this along with adiabatic approach helps in realizing the high speed and low power operation of the binary Vedic multiplier design. The designs are simulated on Cadence Virtuoso Tool using UMC 180 nm CMOS technology. Simulation results show PFAL is the best technology as compared to CMOS, ECRL design for low power implementation of Vedic multiplier.