Electrical Overstress/Electrostatic Discharge Symposium · 2011 · 27 citations · 5 references
EngineeringElectrical EngineeringCircuit TheorySimulation-based DesignCurrent-voltage CharacteristicsElectrical System TestingElectromagnetic CompatibilityPower QualityElectromagnetic Transient SimulationOvervoltage TransientsPackage Parasitics
Based on a mobile reference board a full system ESD IC/board codesign flow was examined. Accurate high current transient models of the components and extracted board parasitics were used to simulate the effect of voltage overshoots during the first peak of the IEC 61000–4–2 pulse
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