2002 · 31 citations · 7 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsAnalog IntegrationCmos Circuit DesignDistortion AnalysisDynamic Power ReductionModulationBandwidthCmos Analog Circuit DesignCmos Analog Integrated CircuitsDynamic RangeModulator DesignPower ConsumptionPower Consumption Optimization
This audio-quality CMOS /spl Sigma//spl Delta/ modulator operates from a 3.3 V supply with 2.3 mW power consumption. The dynamic range is 96 dB over a 20-20000 Hz bandwidth and THD for a 1 kHz maximum input signal is -104 dB. A modulator with power consumption increased to 6.6 mW at the same supply voltage has 10l dB dynamic range and THD<-110 dB, proving the tradeoff between power consumption and performance.
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A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
T.H. Lee, Kevin Donnelly, J. Ho et al. · IEEE Journal of Solid-State Circuits · 1994 · 178 citations
Engineering, Computer Engineering, Electrical Engineering +17
PLL design for a 500 MB/s interface
Mark Horowitz, Ann M. Chan, J. Cobrunson et al. · 1993 · 48 citations
Engineering, Computer Engineering, Electrical Engineering +14
A 500-megabyte/s data-rate 4.5 M DRAM
N. Kushiyama, Shigeo Ohshima, D. Stark et al. · IEEE Journal of Solid-State Circuits · 1993 · 42 citations
Engineering, Computer Engineering, Electrical Engineering +13