Concepedia

Wear-leveling Reliability

Wear-Leveling Reliability is a metric that quantifies the effectiveness and consistency of wear-leveling algorithms in uniformly distributing program and erase cycles across flash memory blocks to prevent premature wear-out of specific cells, thereby extending the operational lifespan of non-volatile storage systems.

15

Publications

669

Citations

54

Authors

32

Institutions

Publications per year

2017–2026

2

Parents

Publications

15

Increasing PCM main memory lifetime

Alexandre Ferreira, Miao Zhou, Santiago Bock et al. · 2010 · 128 citations

, , +15

i<sup>2</sup>WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations

Jue Wang, Xiangyu Dong, Yuan Xie et al. · 2013 · 113 citations

, , +14

A group-based wear-leveling algorithm for large-capacity flash memory storage systems

Dawoon Jung, Yoon-Hee Chae, Heeseung Jo et al. · 2007 · 100 citations

, , +14

Garbage collection and wear leveling for flash memory: Past and future

Ming-Chang Yang, Yu-Ming Chang, Che-Wei Tsao et al. · 2014 · 89 citations

, , +15

FPGA-Based Solid-State Drive Prototyping Platform

Yu Cai, Erich F. Haratsch, Mark P. McCartney et al. · 2011 · 42 citations

, , +17

1–5 of 15

Authors

54

  1. TK
    Tei‐Wei Kuo

    National Taiwan University, Taiwan

    3 publications · 131 citations

    3

    h-index

  2. YC
    Yuan-Hao Chang

    National Taiwan University, Taiwan

    3 publications · 131 citations

    3

    h-index

  3. PH
    Pi-Cheng Hsiu

    National Taiwan University, Taiwan

    1 publications · 25 citations

    1

    h-index

  4. BR
    Bruce R. Childers

    University of Pittsburgh, United States

    1 publications · 128 citations

    1

    h-index

  5. JW
    Jue Wang

    Pennsylvania State University, United States

    1 publications · 113 citations

    1

    h-index

1–5 of 54

Institutions

32

  1. National Taiwan University

    Taipei, Taiwan

    3 h-index

    7 publications

    351 citations

  2. Qualcomm (United States)

    San Diego, United States

    2 h-index

    2 publications

    130 citations

  3. Macronix International (Taiwan)

    Hsinchu, Taiwan

    2 h-index

    4 publications

    228 citations

  4. Pennsylvania State University

    State College, United States

    1 h-index

    2 publications

    226 citations

  5. University of Pittsburgh

    Pittsburgh, United States

    1 h-index

    6 publications

    768 citations

  6. Intel (United States)

    Santa Clara, United States

    1 h-index

    1 publications

    28 citations

  7. Qualcomm (United Kingdom)

    Farnborough, United Kingdom

    1 h-index

    1 publications

    113 citations

  8. University of Chinese Academy of Sciences

    Beijing, China

    1 h-index

    3 publications

    48 citations

1–8 of 32

Venues

  1. IEEE Transactions on Computers

    1 publications · 28 citations

    1

    h-index

  2. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 1 publications · 25 citations

    1

    h-index

  3. Design, Automation, and Test in Europe

    Conference · 1 publications · 17 citations

    1

    h-index

  4. ACM Transactions on Storage

    TOS · 1 publications · 17 citations

    1

    h-index

  5. 1

    h-index

1–5