Two-level Logic Synthesis
Two-Level Logic Synthesis is a logic optimization methodology that minimizes Boolean functions into a sum-of-products or product-of-sums form with exactly two levels of logic gates, typically used to realize area-efficient and speed-predictable combinational circuits in digital design.
67
Publications
5.3K
Citations
122
Authors
65
Institutions
Publications per year
2017–2026
4
Parents
67
Synthesis and optimization of digital circuits
Choice Reviews Online · 1994 · 2.4K citations
Engineering, Computer Engineering, Electrical Engineering +17
M. Momenzadeh, Jing Huang, Mehdi B. Tahoori et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005 · 141 citations
Engineering, Computer Engineering, Electrical Engineering +15
1–5 of 67
122
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University of California, Berkeley, United States
5 publications · 535 citations
5
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4
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4
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4
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1–5 of 122
65
University of California, Berkeley
Berkeley, United States
7 h-index
15 publications
1.4K citations

Silesian University of Technology
Gliwice, Poland
6 h-index
8 publications
197 citations
Columbia University
New York, United States
4 h-index
10 publications
174 citations
University of Illinois Urbana-Champaign
Urbana, United States
3 h-index
7 publications
565 citations

Portland State University
Portland, United States
3 h-index
6 publications
239 citations
AT&T (United States)
Bedminster, United States
3 h-index
4 publications
103 citations
IBM (United States)
Armonk, United States
2 h-index
7 publications
177 citations

University of Pisa
Pisa, Italy
2 h-index
2 publications
41 citations
1–8 of 65
13 publications · 930 citations
13
h-index
6 publications · 141 citations
6
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1 publications · 28 citations
1
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1 publications · 20 citations
1
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JSS · 1 publications · 29 citations
1
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1–5