Two-level Logic Synthesis

Two-Level Logic Synthesis is a logic optimization methodology that minimizes Boolean functions into a sum-of-products or product-of-sums form with exactly two levels of logic gates, typically used to realize area-efficient and speed-predictable combinational circuits in digital design.

67

Publications

5.3K

Citations

122

Authors

65

Institutions

Publications per year

2017–2026

4

Authors

122

  1. DK
    Dariusz Kania

    Silesian University of Technology, Poland

    6 publications · 148 citations

    6

    h-index

  2. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    5 publications · 535 citations

    5

    h-index

  3. SM
    Steven M. Nowick

    Columbia University, United States

    4 publications · 71 citations

    4

    h-index

  4. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    4 publications · 243 citations

    4

    h-index

  5. TV
    Tiziano Villa

    University of California, Berkeley, United States

    4 publications · 507 citations

    4

    h-index

1–5 of 122

Venues

  1. 13

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  2. IEEE Transactions on Computers

    6 publications · 141 citations

    6

    h-index

  3. Analytica Chimica Acta

    1 publications · 28 citations

    1

    h-index

  4. 1

    h-index

  5. Journal of Systems and Software

    JSS · 1 publications · 29 citations

    1

    h-index

1–5