Top-gate Architectures
Top-Gate Architectures is a thin-film transistor configuration in which the gate electrode is deposited above the semiconductor layer, distinguishing it from bottom-gate architectures by enabling enhanced process compatibility with underlying layers and improved environmental stability.
146
Publications
5.7K
Citations
828
Authors
194
Institutions
Publications per year
2017–2026
47
Variants
Top-gate Architecture
Parents
146
Very Large Capacitance Enhancement in a Two-Dimensional Electron System
Lü Li, Christoph Richter, Stefan Paetel et al. · Science · 2011 · 226 citations · Full text
Interplay between Different Magnetisms in Cr-Doped Topological Insulators
Xufeng Kou, Murong Lang, Yabin Fan et al. · ACS Nano · 2013 · 135 citations
1–5 of 146
828
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Hong Kong University of Science and Technology, Hong Kong SAR China
4 publications · 105 citations
4
h-index
1–5 of 828
194

Peking University
Beijing, China
12 h-index
76 publications
3.1K citations

Chinese Academy of Sciences
Beijing, China
9 h-index
42 publications
1.6K citations
Kyung Hee University
Seoul, South Korea
6 h-index
27 publications
1K citations
Fudan University
Shanghai, China
5 h-index
45 publications
1.2K citations

National Yang Ming Chiao Tung University
Hsinchu, Taiwan
5 h-index
17 publications
347 citations
Osaka Prefecture University
Sakai, Japan
5 h-index
21 publications
424 citations

National Taiwan University
Taipei, Taiwan
4 h-index
15 publications
558 citations
State Key Laboratory of ASIC and System
Shanghai, China
4 h-index
39 publications
1.1K citations
1–8 of 194
15 publications · 867 citations
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16 publications · 534 citations
15
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11 publications · 367 citations
11
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9 publications · 285 citations
9
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7 publications · 271 citations
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