Top-gate Architectures

Top-Gate Architectures is a thin-film transistor configuration in which the gate electrode is deposited above the semiconductor layer, distinguishing it from bottom-gate architectures by enabling enhanced process compatibility with underlying layers and improved environmental stability.

146

Publications

5.7K

Citations

828

Authors

194

Institutions

Publications per year

2017–2026

47

Variants

Top-gate Architecture

Authors

828

  1. JJ
    Jin Jang

    Kyung Hee University, South Korea

    5 publications · 199 citations

    5

    h-index

  2. TN
    Takashi Nagase

    Osaka Prefecture University, Japan

    5 publications · 101 citations

    5

    h-index

  3. HN
    Hiroyoshi Naito

    Osaka Prefecture University, Japan

    5 publications · 101 citations

    5

    h-index

  4. TK
    Takashi Kobayashi

    Osaka Prefecture University, Japan

    5 publications · 101 citations

    5

    h-index

  5. LL
    Lei Lü

    Hong Kong University of Science and Technology, Hong Kong SAR China

    4 publications · 105 citations

    4

    h-index

1–5 of 828

Venues

  1. Applied Physics Letters

    15 publications · 867 citations

    16

    h-index

  2. IEEE Electron Device Letters

    16 publications · 534 citations

    15

    h-index

  3. Organic Electronics

    11 publications · 367 citations

    11

    h-index

  4. IEEE Transactions on Electron Devices

    9 publications · 285 citations

    9

    h-index

  5. Nano Letters

    7 publications · 271 citations

    7

    h-index

1–5