Superscalar Execution is a processor microarchitecture technique that belongs to the class of instruction-level parallelism methods, distinguished by its capability to issue and execute multiple instructions per clock cycle through dynamic scheduling and parallel functional units.
195
Publications
10.4K
Citations
498
Authors
130
Institutions
Publications per year
2017–2026
4
Publications
195
Limits of control flow on parallelism
Monica S. Lam, Robert P. Wilson · 1992 · 311 citations
The microarchitecture of superscalar processors
James E. Smith, Gurindar S. Sohi · Proceedings of the IEEE · 1995 · 309 citations · Full text
Memory dependence prediction using store sets
George Chrysos, Joel Emer · 1998 · 291 citations
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Authors
498
- JE
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- AM
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- RM
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- YN
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1–5 of 498
Institutions
130
University of Wisconsin–Madison
Madison, United States
10 h-index
21 publications
3K citations
Carnegie Mellon University
Pittsburgh, United States
10 h-index
19 publications
970 citations
University of Washington
Seattle, United States
8 h-index
25 publications
2.2K citations
Hewlett-Packard (United States)
Palo Alto, United States
7 h-index
16 publications
1K citations
IBM (United States)
Armonk, United States
7 h-index
11 publications
279 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
7 h-index
25 publications
1.1K citations
University of Illinois Urbana-Champaign
Urbana, United States
7 h-index
18 publications
873 citations
Stanford University
Stanford, United States
6 h-index
13 publications
861 citations
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Venues
- International Symposium on Microarchitecture
Conference · 9 publications · 654 citations
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- IEEE Micro
8 publications · 505 citations
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- ACM SIGARCH Computer Architecture News
8 publications · 322 citations
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- IEEE Transactions on Computers
6 publications · 431 citations
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- ACM Transactions on Computer Systems
TOCS · 5 publications · 296 citations
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