Process Variation Delay Modeling
Process Variation Delay Modeling is a delay modeling approach that specifically characterizes the impact of manufacturing-induced parametric fluctuations on signal propagation timing within integrated circuits, distinguishing itself from other delay models by explicitly accounting for process variation as a primary source of timing uncertainty.
107
Publications
5.1K
Citations
269
Authors
89
Institutions
Publications per year
2017–2026
5
Parents
107
Delay variability: sources, impacts and trends
Sani Nassif · 2002 · 230 citations
Engineering, Computer Engineering, Electrical Engineering +17
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89
University of Michigan
Ann Arbor, United States
7 h-index
20 publications
1.9K citations
Arizona State University
Tempe, United States
6 h-index
14 publications
389 citations

Kyoto University
Kyoto, Japan
5 h-index
15 publications
417 citations
University of California, Berkeley
Berkeley, United States
5 h-index
10 publications
264 citations
IBM Research - Austin
Austin, United States
5 h-index
6 publications
531 citations
University of Southern California
Los Angeles, United States
4 h-index
9 publications
475 citations
The University of Texas at Austin
Austin, United States
4 h-index
9 publications
307 citations
IBM (United States)
Armonk, United States
4 h-index
7 publications
138 citations
1–8 of 89
9 publications · 319 citations
9
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Conference · 3 publications · 106 citations
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2 publications · 23 citations
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2 publications · 40 citations
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2 publications · 205 citations
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