Process Variation Delay Modeling

Process Variation Delay Modeling is a delay modeling approach that specifically characterizes the impact of manufacturing-induced parametric fluctuations on signal propagation timing within integrated circuits, distinguishing itself from other delay models by explicitly accounting for process variation as a primary source of timing uncertainty.

107

Publications

5.1K

Citations

269

Authors

89

Institutions

Publications per year

2017–2026

5

Authors

269

  1. DB
    David Blaauw

    University of Michigan, United States

    5 publications · 892 citations

    5

    h-index

  2. DS
    Dennis Sylvester

    University of Michigan, United States

    4 publications · 138 citations

    4

    h-index

  3. SV
    Sarma Vrudhula

    Arizona State University, United States

    4 publications · 129 citations

    4

    h-index

  4. YC
    Yu Cao

    Arizona State University, United States

    4 publications · 208 citations

    4

    h-index

  5. QL
    Qunzeng Liu

    University of Minnesota, United States

    3 publications · 77 citations

    3

    h-index

1–5 of 269

Venues

  1. 9

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  2. Design, Automation, and Test in Europe

    Conference · 3 publications · 106 citations

    3

    h-index

  3. 2

    h-index

  4. IEEE Journal of Solid-State Circuits

    2 publications · 40 citations

    2

    h-index

  5. 2

    h-index

1–5