Post-Placement Timing Analysis is a timing analysis methodology in electronic design automation that evaluates the timing behavior of a digital circuit after the placement phase, distinguishing itself by incorporating estimated interconnect delays based on physical placement prior to routing.
9
Publications
581
Citations
23
Authors
10
Institutions
Publications per year
2017–2026
0
Parents
Publications
9
1–5 of 9
Authors
23
- SD
2
h-index
- DP
2
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- CG
2
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- DP
2
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- MJ
2
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1–5 of 23
Institutions
10
Pennsylvania State University
State College, United States
2 h-index
2 publications
304 citations
Boston College
Boston, United States
2 h-index
2 publications
304 citations
University of Rochester
Rochester, United States
2 h-index
2 publications
304 citations
Intel (United States)
Santa Clara, United States
1 h-index
1 publications
11 citations
University of Toronto
Toronto, Canada
1 h-index
2 publications
108 citations
Massachusetts Institute of Technology
Cambridge, United States
1 h-index
2 publications
148 citations
Cadence Design Systems (United States)
San Jose, United States
1 h-index
3 publications
255 citations
University of California, Riverside
Riverside, United States
1 h-index
2 publications
46 citations
1–8 of 10
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 23 citations
1
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- SSRN Electronic Journal
Repository · 1 publications · 41 citations
1
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- Journal of Corporate Finance
1 publications · 263 citations
1
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- International Journal on Advanced Science Engineering and Information Technology
IJASEIT · 1 publications · 11 citations
1
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- ACM Transactions on Design Automation of Electronic Systems
TODAES · 1 publications · 18 citations
1–5