Post-layout Optimization

Post-Layout Optimization is a physical design methodology that refines and enhances the performance, power, area, or timing characteristics of an integrated circuit after the layout phase by incorporating parasitic effects and geometric constraints to achieve sign-off quality implementation.

104

Publications

3.3K

Citations

293

Authors

108

Institutions

Publications per year

2017–2026

Variants

Post-layout Refinement

Parents

Physical Design

Publications

104

Improvement of the quality factor of RF integrated inductors by layout optimization

J.M. López-Villegas, Josep Samitier, C. Cané et al. · IEEE Transactions on Microwave Theory and Techniques · 2000 · 271 citations · Full text

Engineering, Electrical Engineering, Design Optimization +16

A survey of optimization techniques for integrated-circuit design

Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni‐Vincentelli · Proceedings of the IEEE · 1981 · 264 citations

Engineering, Computer Engineering, Electrical Engineering +14

Layout impact of resolution enhancement techniques

Lars W. Liebmann · 2003 · 114 citations

Engineering, Computer Engineering, Optoelectronics +14

Redundant-via enhanced maze routing for yield improvement

Gang Xu, Lida Huang, David Z. Pan et al. · 2005 · 88 citations

Computing, Computational Engineering, Algorithmic Design +16

A study of the residue-to-binary converters for the three-moduli sets

Wei Wang, M. N. S. Swamy, M.O. Ahmad et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2003 · 85 citations

Engineering, Computer Engineering, Computer Science +13

1–5 of 104

Authors

293

DZ
David Z. Pan
The University of Texas at Austin, United States
11 publications · 494 citations
11
h-index
YC
Yao‐Wen Chang
National Taiwan University, Taiwan
6 publications · 162 citations
6
h-index
NS
Nan Sun
The University of Texas at Austin, United States
5 publications · 156 citations
5
h-index
LB
Luca Benini
University of Bologna, Italy
4 publications · 146 citations
4
h-index
XT
Xiyuan Tang
The University of Texas at Austin, United States
4 publications · 131 citations
4
h-index

1–5 of 293

Institutions

108

1–8 of 108

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
5 publications · 229 citations
5
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
5 publications · 117 citations
5
h-index
IEEE Transactions on Circuits and Systems I Regular Papers
3 publications · 105 citations
3
h-index
Microelectronics Journal
2 publications · 22 citations
2
h-index
Microelectronics Reliability
2 publications · 24 citations
2
h-index

1–5