Pipeline Hazards
Pipeline Hazards is a phenomenon in instruction-level parallelism that disrupts the normal flow of pipeline stages, arising from data dependencies, resource conflicts, or control dependencies that prevent the overlapping execution of instructions in a pipelined processor.
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304
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149
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2017–2026
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The Pipeline Is Leaking Women All the Way Along
Bounding pipeline and instruction cache performance
Christopher Healy, Robert D. Arnold, Frank Mueller et al. · IEEE Transactions on Computers · 1999 · 206 citations
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149

China University of Petroleum, Beijing
Beijing, China
4 h-index
13 publications
322 citations
Sinopec (China)
Beijing, China
3 h-index
5 publications
107 citations
Hewlett-Packard (United States)
Palo Alto, United States
3 h-index
3 publications
88 citations

Southwest Jiaotong University
Chengdu, China
3 h-index
10 publications
200 citations

Sapienza University of Rome
Rome, Italy
3 h-index
5 publications
370 citations

University of Electronic Science and Technology of China
Chengdu, China
2 h-index
3 publications
55 citations
Florida State University
Tallahassee, United States
2 h-index
4 publications
748 citations
Florida Agricultural and Mechanical University
Tallahassee, United States
2 h-index
2 publications
374 citations
1–8 of 149
10 publications · 513 citations
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5 publications · 176 citations
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3 publications · 87 citations
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3 publications · 141 citations
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2 publications · 55 citations
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