Young Hyun Bae

An accurate worst case timing analysis for RISC processors

Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang et al. · IEEE Transactions on Software Engineering · 1995 · 246 citations

Engineering, Timing Schema, Computer Architecture +23

An accurate worst case timing analysis technique for RISC processors

Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang et al. · 1994 · 122 citations

Engineering, Timing Schema, Computer Architecture +24

Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture

Yoon Jae Seong, Eyee Hyun Nam, Jin Hyuk Yoon et al. · IEEE Transactions on Computers · 2010 · 87 citations

Hardware Security, Storage Performance, Engineering +10

Worst case timing analysis of RISC processors: R3000/R3010 case study

Y. Hur, Young Hyun Bae, Sung-Soo Lim et al. · 2002 · 41 citations

Engineering, Timing Schema, Computer Architecture +21

A dual-mode instruction prefetch scheme for improved worst case and average case program execution times

Mi Kyeong Lee, Sang Lyul Min, C.Y. Park et al. · 2002 · 20 citations

Engineering, Worst Case, Computer Architecture +24