Physical Verification
Physical Verification is a formal methodology within the domain of integrated circuit design that ensures the correctness and manufacturability of a physical layout by verifying its adherence to geometric, connectivity, and electrical constraints specified by the foundry process design rules.
84
Publications
3K
Citations
289
Authors
101
Institutions
Publications per year
2017–2026
33
Variants
Physical Design Verification
Parents
84
Double patterning design split implementation and validation for the 32nm node
Martin Drapeau, Vincent Wiaux, Eric Hendrickx et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 95 citations
Engineering, Computer Engineering, Computer-aided Design +13
1–5 of 84
289
12
h-index
12
h-index
5
h-index
5
h-index
5
h-index
1–5 of 289
101
The University of Texas at Austin
Austin, United States
12 h-index
41 publications
2.1K citations
Chinese University of Hong Kong
Hong Kong, Hong Kong
7 h-index
21 publications
1.4K citations
Mentor Technologies
Tulsa, United States
7 h-index
13 publications
513 citations
Siemens (Hungary)
Budapest, Hungary
5 h-index
9 publications
289 citations
Toshiba (Japan)
Tokyo, Japan
5 h-index
13 publications
584 citations
Fudan University
Shanghai, China
5 h-index
11 publications
394 citations
Shanghai Fudan Microelectronics (China)
Shanghai, China
4 h-index
9 publications
358 citations
STMicroelectronics (France)
Montrouge, France
3 h-index
6 publications
138 citations
1–8 of 101
10 publications · 400 citations
10
h-index
5 publications · 333 citations
5
h-index
PNAS · 2 publications · 60 citations
2
h-index
2 publications · 52 citations
2
h-index
2 publications · 146 citations
2
h-index
1–5