Physical Verification

Physical Verification is a formal methodology within the domain of integrated circuit design that ensures the correctness and manufacturability of a physical layout by verifying its adherence to geometric, connectivity, and electrical constraints specified by the foundry process design rules.

84

Publications

3K

Citations

289

Authors

101

Institutions

Publications per year

2017–2026

33

Variants

Physical Design Verification

Authors

289

  1. DZ
    David Z. Pan

    The University of Texas at Austin, United States

    12 publications · 634 citations

    12

    h-index

  2. BY
    Bei Yu

    Chinese University of Hong Kong, Hong Kong SAR China

    12 publications · 757 citations

    12

    h-index

  3. TM
    Tetsuaki Matsunawa

    Toshiba (Japan), Japan

    5 publications · 266 citations

    5

    h-index

  4. YL
    Yibo Lin

    Peking University, China

    5 publications · 190 citations

    5

    h-index

  5. XZ
    Xuan Zeng

    Fudan University, China

    5 publications · 196 citations

    5

    h-index

1–5 of 289

Venues

  1. 10

    h-index

  2. 5

    h-index

  3. Proceedings of the National Academy of Sciences

    PNAS · 2 publications · 60 citations

    2

    h-index

  4. Modeling of systems and processes

    2 publications · 52 citations

    2

    h-index

  5. Engineering With Computers

    2 publications · 146 citations

    2

    h-index

1–5