Multi-threshold Voltage Design
Multi-Threshold Voltage Design is a low-power integrated circuit design methodology that employs transistors with multiple threshold voltage levels to optimize the trade-off between leakage power and performance in power-gated systems.
47
Publications
1.4K
Citations
245
Authors
59
Institutions
Publications per year
2017–2026
12
Parents
47
1–5 of 47
245
5
h-index
3
h-index
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h-index
Commissariat à l'Énergie Atomique et aux Énergies Alternatives, France
2 publications · 40 citations
2
h-index
1–5 of 245
59
IBM (United States)
Armonk, United States
5 h-index
70 publications
1.7K citations
University of Wisconsin–Madison
Madison, United States
4 h-index
5 publications
140 citations

Hong Kong University of Science and Technology
Hong Kong, Hong Kong
4 h-index
5 publications
124 citations
Intel (United States)
Santa Clara, United States
3 h-index
6 publications
388 citations
University of Southern California
Los Angeles, United States
3 h-index
13 publications
599 citations
Pohang University of Science and Technology
Pohang, South Korea
2 h-index
5 publications
337 citations
Purdue University West Lafayette
West Lafayette, United States
2 h-index
3 publications
192 citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
2 h-index
8 publications
110 citations
1–8 of 59
4 publications · 198 citations
4
h-index
2 publications · 49 citations
2
h-index
2 publications · 41 citations
2
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2 publications · 102 citations
2
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1 publications · 18 citations
1
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1–5