Lut-based Logic Optimization

LUT-Based Logic Optimization is a computational method in digital circuit design that optimizes logic functions by minimizing and restructuring Boolean expressions specifically for implementation in Lookup Tables, distinguishing it from other logic optimization techniques by its direct alignment with the architectural constraints and capabilities of LUT-based reconfigurable devices.

164

Publications

5.7K

Citations

383

Authors

151

Institutions

Publications per year

2017–2026

39

Authors

383

  1. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    7 publications · 606 citations

    7

    h-index

  2. JC
    Jason Cong

    University of California, Los Angeles, United States

    7 publications · 369 citations

    7

    h-index

  3. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    7 publications · 432 citations

    7

    h-index

  4. MS
    Mathias Soeken

    École Polytechnique Fédérale de Lausanne, Switzerland

    6 publications · 251 citations

    6

    h-index

  5. AM
    Alan Mishchenko

    University of California, Berkeley, United States

    6 publications · 434 citations

    6

    h-index

1–5 of 383

Venues

  1. 7

    h-index

  2. 6

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  3. Integration

    5 publications · 128 citations

    5

    h-index

  4. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 2 publications · 151 citations

    3

    h-index

  5. Microprocessors and Microsystems

    MICPRO · 3 publications · 81 citations

    3

    h-index

1–5