Lut-based Logic Optimization
LUT-Based Logic Optimization is a computational method in digital circuit design that optimizes logic functions by minimizing and restructuring Boolean expressions specifically for implementation in Lookup Tables, distinguishing it from other logic optimization techniques by its direct alignment with the architectural constraints and capabilities of LUT-based reconfigurable devices.
164
Publications
5.7K
Citations
383
Authors
151
Institutions
Publications per year
2017–2026
39
Parents
164
Improved logic synthesis algorithms for table look up architectures
Rajeev Murgai, Narendra Shenoy, Robert K. Brayton et al. · 2002 · 209 citations
1–5 of 164
383
7
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7
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École Polytechnique Fédérale de Lausanne, Switzerland
7 publications · 432 citations
7
h-index
6
h-index
6
h-index
1–5 of 383
151
University of California, Los Angeles
Los Angeles, United States
13 h-index
29 publications
929 citations

University of Toronto
Toronto, Canada
9 h-index
15 publications
1.4K citations
University of California, Berkeley
Berkeley, United States
7 h-index
17 publications
1.9K citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
7 h-index
18 publications
1.2K citations
Tsinghua University
Beijing, China
5 h-index
21 publications
932 citations
Nanyang Technological University
Singapore, Singapore
4 h-index
6 publications
189 citations
University of Illinois Urbana-Champaign
Urbana, United States
4 h-index
5 publications
110 citations
Institute for Infocomm Research
Singapore, Singapore
3 h-index
3 publications
154 citations
1–8 of 151
7 publications · 635 citations
7
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6 publications · 551 citations
6
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5 publications · 128 citations
5
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TODAES · 2 publications · 151 citations
3
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MICPRO · 3 publications · 81 citations
3
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1–5