Concepedia

Load-store Unit Design

Load-Store Unit Design is a processor microarchitecture component design that orchestrates data transfers between the CPU core and memory hierarchy by specifically managing load (read) and store (write) operations with precision, timing, and concurrency distinct from other execution units.

24

Publications

1.1K

Citations

84

Authors

25

Institutions

Publications per year

2017–2026

0

Parents

Publications

24

Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

G. Semeraro, Grigorios Magklis, Rajeev Balasubramonian et al. · 2004 · 370 citations

, , +17

Design models for unit load storage and retrieval systems using autonomous vehicle technology and resource conserving storage and dwell point policies

Po-Hsun Kuo, Ananth Krishnamurthy, Charles J. Malmborg · Applied Mathematical Modelling · 2006 · 135 citations

, , +17

Advanced performance features of the 64-bit PA-8000

David Hunt · 2002 · 125 citations

, , +17

The TM3270 Media-Processor

Jan-Willem van de Waerdt, S. Vassiliadis, Shirshendu Das et al. · 2006 · 78 citations · Full text

, , +17

Scalable Load and Store Processing in Latency Tolerant Processors

Amit Gandhi, Haitham Akkary, Ravi Rajwar et al. · 2005 · 50 citations

, , +17

1–5 of 24

Authors

84

  1. TU
    Theo Ungerer

    University of Augsburg, Germany

    3 publications · 50 citations

    3

    h-index

  2. ST
    Srikanth T. Srinivasan

    Intel (United States), United States

    2 publications · 97 citations

    2

    h-index

  3. KL
    Konrad Lai

    Intel (United States), United States

    2 publications · 97 citations

    2

    h-index

  4. AG
    Amit Gandhi

    Portland State University, United States

    2 publications · 97 citations

    2

    h-index

  5. RR
    Ravi Rajwar

    Intel (United States), United States

    2 publications · 97 citations

    2

    h-index

1–5 of 84

Institutions

25

  1. University of Rochester

    Rochester, United States

    3 h-index

    10 publications

    2.3K citations

  2. Karlsruhe Institute of Technology

    Karlsruhe, Germany

    3 h-index

    4 publications

    66 citations

  3. Hewlett-Packard (United States)

    Palo Alto, United States

    2 h-index

    3 publications

    169 citations

  4. Engineering Systems (United States)

    Omaha, United States

    2 h-index

    4 publications

    530 citations

  5. Portland State University

    Portland, United States

    2 h-index

    2 publications

    97 citations

  6. Delft University of Technology

    Delft, The Netherlands

    1 h-index

    2 publications

    156 citations

  7. University of Pennsylvania

    Philadelphia, United States

    1 h-index

    1 publications

    17 citations

  8. Rensselaer Polytechnic Institute

    Troy, United States

    1 h-index

    3 publications

    405 citations

1–8 of 25

Venues

  1. International Journal of Parallel Programming

    1 publications · 10 citations

    1

    h-index

  2. IBM Journal of Research and Development

    1 publications · 40 citations

    1

    h-index

  3. ACM SIGARCH Computer Architecture News

    1 publications · 47 citations

    1

    h-index

  4. ScholarlyCommons (University of Pennsylvania)

    Repository · 1 publications · 17 citations

    1

    h-index

  5. 1

    h-index

1–5