Concepedia

Latch Optimization

Latch Optimization is a logic synthesis technique that minimizes the number or area of latches in a digital circuit while preserving its sequential behavior and timing constraints.

31

Publications

1.6K

Citations

64

Authors

31

Institutions

Publications per year

2017–2026

1

Parents

Publications

31

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Vladimir Stojanović, Vojin G. Oklobdzija · IEEE Journal of Solid-State Circuits · 1999 · 618 citations

, , +17

Computing optimal clock schedules

Thomas G. Szymanski · Design Automation Conference · 1992 · 101 citations

, , +17

Computing optimal clock schedules

Thomas G. Szymanski · [1992] Proceedings 29th ACM/IEEE Design Automation Conference · 2003 · 83 citations

, , +17

Optimization of reversible sequential circuits

Abu Sadat Md. Sayem, Masashi Ueda · arXiv (Cornell University) · 2010 · 69 citations · Full text

, , +16

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs

Himanshu Thapliyal, N. Ranganathan · 2010 · 56 citations

, , +13

1–5 of 31

Authors

64

  1. YS
    Youngsoo Shin

    Korea Advanced Institute of Science and Technology, South Korea

    3 publications · 71 citations

    3

    h-index

  2. ES
    Ellen Sentovich

    Lawrence Berkeley National Laboratory, United States

    3 publications · 82 citations

    3

    h-index

  3. HT
    Horia Toma

    École Nationale Supérieure des Mines de Paris, France

    3 publications · 82 citations

    3

    h-index

  4. SP
    Seungwhun Paik

    Korea Advanced Institute of Science and Technology, South Korea

    2 publications · 46 citations

    2

    h-index

  5. GB
    Gérard Berry

    École Nationale Supérieure des Mines de Paris, France

    2 publications · 69 citations

    2

    h-index

1–5 of 64

Institutions

31

  1. Korea Advanced Institute of Science and Technology

    Daejeon, South Korea

    4 h-index

    11 publications

    242 citations

  2. École Nationale Supérieure des Mines de Paris

    Paris, France

    3 h-index

    8 publications

    233 citations

  3. Centre de Mathématiques Appliquées de l'École polytechnique

    Palaiseau, France

    2 h-index

    6 publications

    207 citations

  4. University of Southampton

    Southampton, United Kingdom

    2 h-index

    4 publications

    64 citations

  5. IBM (United States)

    Armonk, United States

    2 h-index

    2 publications

    55 citations

  6. Pennsylvania State University

    State College, United States

    2 h-index

    4 publications

    64 citations

  7. Anhui University

    Hefei, China

    1 h-index

    2 publications

    82 citations

  8. Mazandaran University of Science and Technology

    Babol, Iran

    1 h-index

    2 publications

    58 citations

1–8 of 31

Venues

  1. Microelectronics Reliability

    4 publications · 153 citations

    4

    h-index

  2. IEEE Journal of Solid-State Circuits

    2 publications · 669 citations

    2

    h-index

  3. 1

    h-index

  4. [1992] Proceedings 29th ACM/IEEE Design Automation Conference

    Conference · 1 publications · 83 citations

    1

    h-index

  5. 1

    h-index

1–5