Concepedia

Issue Queue Design

Issue Queue Design is a processor microarchitecture construct that organizes and manages instruction dispatch logic in out-of-order execution engines by determining the readiness and selection of instructions for execution units within a superscalar pipeline.

33

Publications

1.6K

Citations

53

Authors

21

Institutions

Publications per year

2017–2026

3

Variants

Instruction Issue Queue Design

Parents

Publications

33

A large, fast instruction window for tolerating cache misses

Alvin R. Lebeck, Jinson Koppanalil, Tong Li et al. · ACM SIGARCH Computer Architecture News · 2002 · 180 citations

, , +17

Power and energy reduction via pipeline balancing

R. Iris Bahar, Srilatha Manne · 2001 · 168 citations

, , +17

Front-end policies for improved issue efficiency in SMT processors

David H. Albonesi · 2003 · 107 citations

, , +13

A circuit level implementation of an adaptive issue queue for power-aware microprocessors

Alper Buyuktosunoglu, David H. Albonesi, S.E. Schuster et al. · 2001 · 91 citations

, , +7

Reducing design complexity of the load/store queue

Il Memming Park, Chong Liang Ooi, T. N. Vijaykumar · 2003 · 90 citations

, , +17

1–5 of 33

Authors

53

  1. DP
    Dmitry Ponomarev

    Binghamton University, United States

    5 publications · 141 citations

    5

    h-index

  2. DH
    David H. Albonesi

    University of Rochester, United States

    4 publications · 261 citations

    5

    h-index

  3. PB
    Pradip Bose

    IBM Research - Thomas J. Watson Research Center, United States

    3 publications · 170 citations

    4

    h-index

  4. AB
    Alper Buyuktosunoglu

    IBM (United States), United States

    3 publications · 154 citations

    4

    h-index

  5. AG
    Antonio González

    Universitat Politècnica de Catalunya, Spain

    3 publications · 72 citations

    3

    h-index

1–5 of 53

Institutions

21

  1. Binghamton University

    Binghamton, United States

    7 h-index

    19 publications

    548 citations

  2. University of Rochester

    Rochester, United States

    4 h-index

    9 publications

    546 citations

  3. University of Notre Dame

    Notre Dame, United States

    3 h-index

    3 publications

    96 citations

  4. Universitat Politècnica de Catalunya

    Barcelona, Spain

    3 h-index

    9 publications

    211 citations

  5. PQ Corporation (Canada)

    Toronto, Canada

    2 h-index

    2 publications

    254 citations

  6. University of Virginia

    Charlottesville, United States

    2 h-index

    4 publications

    160 citations

  7. North Carolina State University

    Raleigh, United States

    2 h-index

    4 publications

    526 citations

  8. John Brown University

    Siloam Springs, United States

    2 h-index

    2 publications

    254 citations

1–8 of 21

Venues

  1. 2

    h-index

  2. IEEE Micro

    1 publications · 33 citations

    1

    h-index

  3. IEEE Transactions on Computers

    1 publications · 29 citations

    1

    h-index

  4. ACM SIGARCH Computer Architecture News

    1 publications · 180 citations

    1

    h-index

  5. OSF Preprints (OSF Preprints)

    Repository · 1 publications · 14 citations

    1

    h-index

1–5