I/o Buffer Design

I/O Buffer Design is a hardware architecture methodology that specifies the structure, organization, and management of temporary storage elements used to reconcile speed, timing, and data format mismatches between input/output devices and a computer system’s central processing unit or memory subsystem.

47

Publications

1.4K

Citations

128

Authors

45

Institutions

Publications per year

2017–2026

1

Authors

128

  1. MK
    Ming‐Dou Ker

    National Yang Ming Chiao Tung University, Taiwan

    6 publications · 162 citations

    6

    h-index

  2. AC
    Alok Choudhary

    Northwestern University, United States

    1 publications · 30 citations

    2

    h-index

  3. PD
    Peter Druschel

    Rice University, United States

    2 publications · 294 citations

    2

    h-index

  4. TG
    T. Gabara

    AT&T (United States), United States

    2 publications · 45 citations

    2

    h-index

  5. JC
    José C. Pedro

    University of Aveiro, Portugal

    2 publications · 33 citations

    2

    h-index

1–5 of 128

Venues

  1. IEEE Journal of Solid-State Circuits

    4 publications · 156 citations

    4

    h-index

  2. 3

    h-index

  3. Journal of Parallel and Distributed Computing

    2 publications · 38 citations

    2

    h-index

  4. IEEE Intelligent Vehicles Symposium

    IV · 1 publications · 23 citations

    1

    h-index

  5. Design Automation Conference

    Conference · 1 publications · 13 citations

    1

    h-index

1–5