Error Detection For Configuration Memory
Error Detection for Configuration Memory is a methodological framework designed to identify unintended alterations or corruption in the configuration data of programmable logic devices, distinguishing itself by targeting memory integrity verification specifically within the configuration stream rather than operational data.
8
Publications
206
Citations
27
Authors
8
Institutions
Publications per year
2017–2026
2
Parents
8
Detecting SEU-caused routing errors in SRAM-based FPGAs
E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth et al. · 2005 · 27 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 8
27
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8
Universidad Nebrija
Madrid, Spain
2 h-index
6 publications
240 citations

Indian Institute of Technology Madras
Chennai, India
1 h-index
4 publications
108 citations

Pennsylvania State University
State College, United States
1 h-index
1 publications
27 citations

University of Piraeus
Piraeus, Greece
1 h-index
3 publications
57 citations
Politecnico di Torino
Turin, Italy
1 h-index
3 publications
63 citations
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
1 h-index
3 publications
39 citations
Institut Polytechnique de Bordeaux
Bordeaux, France
1 h-index
2 publications
26 citations
Laboratoire de l'Intégration du Matériau au Système
Talence, France
1 h-index
2 publications
26 citations
1–8 of 8
1 publications · 36 citations
1
h-index
1 publications · 13 citations
1
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Repository · 1 publications · 13 citations
1
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1 publications · 44 citations
1
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MICPRO · 1 publications · 13 citations
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