Error Detection For Configuration Memory

Error Detection for Configuration Memory is a methodological framework designed to identify unintended alterations or corruption in the configuration data of programmable logic devices, distinguishing itself by targeting memory integrity verification specifically within the configuration stream rather than operational data.

8

Publications

206

Citations

27

Authors

8

Institutions

Publications per year

2017–2026

2

Authors

27

  1. LA
    Luis Alberto Aranda

    Universidad Nebrija, Spain

    2 publications · 80 citations

    2

    h-index

  2. JA
    Juan Antonio Maestro

    Universidad Nebrija, Spain

    2 publications · 80 citations

    2

    h-index

  3. AS
    Alfonso Sánchez‐Macián

    Universidad Nebrija, Spain

    1 publications · 44 citations

    1

    h-index

  4. CW
    Chen Wei Tseng

    Xilinx (United States), United States

    1 publications · 33 citations

    1

    h-index

  5. LS
    Luca Sterpone

    Politecnico di Torino, Italy

    1 publications · 21 citations

    1

    h-index

1–5 of 27

Venues

  1. IEEE Transactions on Nuclear Science

    1 publications · 36 citations

    1

    h-index

  2. Microelectronics Reliability

    1 publications · 13 citations

    1

    h-index

  3. ScholarsArchive (Brigham Young University)

    Repository · 1 publications · 13 citations

    1

    h-index

  4. IEEE Access

    1 publications · 44 citations

    1

    h-index

  5. Microprocessors and Microsystems

    MICPRO · 1 publications · 13 citations

1–5