Juan Antonio Maestro

Author

Universidad Nebrija ORCID

Also Known As

J A Maestro, J. A. Maestro, J. Maestro, J.A. Maestro, Juan A. Maestro, Juan Antonio Maestro, Juan Maestro

209

Publications

3.3K

Citations

H-Index

107

Concepts

All Affiliations

Universidad Nebrija Universidad Carlos III de Madrid University of Rome Tor Vergata University College Dublin Consorzio Nazionale Interuniversitario per le Telecomunicazioni

About

Juan Antonio Maestro is an author at Universidad Nebrija specializing in engineering, computer engineering, and hardware security.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	78	2.7K
2	Computer Engineering	30	77	2.7K
3	Computer Science	27	62	1.8K
4	Social Sciences	1	1	39
5	Data Science	1	1	13

Juan Antonio Maestro

Publications

2.8K

Citations

H-Index

Page 1

	Year	Citations
IEEE 802.3az: the road to energy efficient ethernet Ken Christensen, Pedro Reviriego, Bruce Nordman, IEEE Communications Magazine Energy ConsumptionTime-sensitive NetworkingEngineeringEnergy EfficiencyEdge Computing	2010	316
Performance evaluation of energy efficient ethernet Pedro Reviriego, José Alberto Hernández, David Larrabeiti, IEEE Communications Letters Electrical EngineeringPower-aware ComputingEngineeringEnergy EfficiencyEnergy Management	2009	143
An Initial Evaluation of Energy Efficient Ethernet Pedro Reviriego, Ken Christensen, J Rabanillo, IEEE Communications Letters Electrical EngineeringNew StandardSeptember 2010Energy Efficient EthernetSmart Grid	2011	101
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications Shih‐Fu Liu, Pedro Reviriego, Juan Antonio Maestro IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringError Control TechniqueMem TestingVerificationComputer Architecture	2010	90
Burst Transmission in Energy Efficient Ethernet Pedro Reviriego, Jose-Alberto Hernadez, David Larrabeiti, IEEE Internet Computing Energy ConsumptionTime-sensitive NetworkingEngineeringHigh Performance Computer NetworkEdge Computing	2010	85
Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes Through Selective Shortening and Bit Placement Alfonso Sánchez‐Macián, Pedro Reviriego, Juan Antonio Maestro IEEE Transactions on Device and Materials Reliability EngineeringError Control TechniqueMem TestingComputer ArchitectureBit Placement	2012	78
Reliability Analysis of Memories Suffering Multiple Bit Upsets Pedro Reviriego, Juan Antonio Maestro, Catalina Cervantes IEEE Transactions on Device and Materials Reliability Mean TimeEngineeringMem TestingComputer ArchitectureHardware Security	2007	67
A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs O. Ruano, Juan Antonio Maestro, Pedro Reviriego IEEE Transactions on Nuclear Science Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignCircuit Design	2009	67
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction Luis-J. Saiz-Adalid, Pedro Reviriego, Pedro Gil, IEEE Transactions on Very Large Scale Integration (VLSI) Systems New CodesVlsi DesignEngineeringError Control TechniqueComputer Architecture	2014	60
Matrix-Based Codes for Adjacent Error Correction Costas Argyrides, Pedro Reviriego, Dhiraj K. Pradhan, IEEE Transactions on Nuclear Science Hardware SecurityAdjacent Error CorrectionElectrical EngineeringError DetectionEngineering	2010	51

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