Device-Level Electrostatic Discharge is an academic concept that refers to a discrete methodological or theoretical contribution specifically designed to model, analyze, or mitigate electrostatic discharge phenomena at the individual semiconductor device level within the broader field of electrostatic discharge protection.
33
Publications
1K
Citations
88
Authors
34
Institutions
Publications per year
2017–2026
1
Publications
33
1–5 of 33
Authors
88
- SH
8
h-index
- JV
2
h-index
- TL
2
h-index
- WG
2
h-index
- JJ
2
h-index
1–5 of 88
Institutions
34
IBM (United States)
Armonk, United States
9 h-index
19 publications
576 citations
AT&T (United States)
Bedminster, United States
4 h-index
8 publications
165 citations
Nokia (United States)
Coppell, United States
2 h-index
3 publications
53 citations
University of Central Florida
Orlando, United States
2 h-index
2 publications
220 citations
University of Illinois Urbana-Champaign
Urbana, United States
2 h-index
3 publications
62 citations
IBM Research - Austin
Austin, United States
2 h-index
2 publications
38 citations
Western University
London, Canada
2 h-index
2 publications
61 citations
Infineon Technologies (Germany)
Munich, Germany
1 h-index
3 publications
33 citations
1–8 of 34
Venues
- Journal of Electrostatics
6 publications · 208 citations
6
h-index
- Reliability physics
2 publications · 45 citations
2
h-index
- Microelectronics Reliability
2 publications · 54 citations
2
h-index
- Proceedings of the IEEE
2 publications · 220 citations
2
h-index
- IEEE Transactions on Electron Devices
1 publications · 11 citations
1
h-index
1–5