Clock Tree Power Reduction

Clock Tree Power Reduction is a dynamic power optimization technique that specifically targets the minimization of power consumption in the clock distribution network of a synchronous digital circuit by leveraging structural and operational modifications to the clock tree.

132

Publications

4.7K

Citations

384

Authors

125

Institutions

Publications per year

2017–2026

Parents

Dynamic Power Reduction

Publications

132

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, M. Igarashi, F. Minami et al. · IEEE Journal of Solid-State Circuits · 1998 · 276 citations

Engineering, Computer Engineering, Electrical Engineering +17

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

Hamid Mahmoodi, Vishwanadh Tirumalashetty, Matthew Cooke et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2008 · 161 citations

Engineering, Computer Engineering, Electrical Engineering +17

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

Ahmed Hemani, T. Meincke, S. Kumar et al. · 1999 · 150 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +16

Reducing power dissipation during test using scan chain disable

Rajkumar Sankaralingam, B. Pouya, Nur A. Touba · 2002 · 150 citations

Engineering, Computer Engineering, Computer Science +17

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Yannick Bonhomme, Patrick Girard, L. Guiller et al. · 2002 · 141 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 132

Authors

384

MP
Massoud Pedram
University of Southern California, United States
5 publications · 169 citations
5
h-index
SK
Sung Kyu Lim
Georgia Institute of Technology, United States
4 publications · 120 citations
4
h-index
DZ
David Z. Pan
The University of Texas at Austin, United States
4 publications · 66 citations
4
h-index
MS
Majid Sarrafzadeh
University of California, Los Angeles, United States
3 publications · 207 citations
3
h-index
LB
Luca Benini
University of Bologna, Italy
3 publications · 148 citations
3
h-index

1–5 of 384

Institutions

125

1–8 of 125

Venues

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
14 publications · 708 citations
13
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
8 publications · 381 citations
8
h-index
ACM Transactions on Design Automation of Electronic Systems
TODAES · 4 publications · 60 citations
4
h-index
IEEE Journal of Solid-State Circuits
4 publications · 421 citations
4
h-index
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 2 publications · 40 citations
2
h-index

1–5