Clock Management Units

Clock Management Units is a specialized circuitry within a Field-Programmable Gate Array architecture that regulates, distributes, and synthesizes clock signals to ensure precise timing coordination across programmable logic elements, distinguished by its ability to dynamically adjust frequency, phase, and duty cycle through on-chip phase-locked or delay-locked loop mechanisms.

87

Publications

2.8K

Citations

307

Authors

82

Institutions

Publications per year

2017–2026

14

Authors

307

  1. SL
    Shen-Iuan Liu

    National Taiwan University, Taiwan

    4 publications · 146 citations

    4

    h-index

  2. CK
    Chulwoo Kim

    Korea University, South Korea

    3 publications · 51 citations

    3

    h-index

  3. ZW
    Zhihua Wang

    Tsinghua University, China

    2 publications · 57 citations

    3

    h-index

  4. TB
    Thomas Byunghak Cho

    Samsung (South Korea), South Korea

    2 publications · 53 citations

    3

    h-index

  5. XX
    Xiang Xie

    Tsinghua University, China

    3 publications · 178 citations

    3

    h-index

1–5 of 307

Venues

  1. IEEE Journal of Solid-State Circuits

    15 publications · 935 citations

    14

    h-index

  2. 4

    h-index

  3. IEEE Transactions on Power Electronics

    2 publications · 93 citations

    3

    h-index

  4. 3

    h-index

  5. 2

    h-index

1–5