Thomas Byunghak Cho

A 28-nm 75-fs_rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Wanghua Wu, Chih-Wei Yao, Kunal Godbole et al. · IEEE Journal of Solid-State Circuits · 2019 · 192 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Wanghua Wu, Chih-Wei Yao, Chengkai Guo et al. · IEEE Journal of Solid-State Circuits · 2021 · 133 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 14-nm 0.14-ps_rmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Chih-Wei Yao, Ronghua Ni, Chung Lau et al. · IEEE Journal of Solid-State Circuits · 2017 · 72 citations

Engineering, Electrical Engineering, Analog Electronics +16

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

Jongwoo Lee, Ki Yong Son, Hyung-sun Lim et al. · IEEE Journal of Solid-State Circuits · 2019 · 61 citations

Engineering, Communication, Electrical Engineering +17

32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels

Wanghua Wu, Chih-Wei Yao, Chengkai Guo et al. · 2021 · 58 citations

Engineering, Electrical Engineering, Analog Electronics +16