Concepedia

Clock Gating Optimization

Clock Gating Optimization is a power management technique that selectively disables the clock signal to idle circuit components by inserting gating logic, thereby reducing dynamic power consumption without altering the functional behavior of the synchronous digital system.

22

Publications

914

Citations

95

Authors

41

Institutions

Publications per year

2017–2026

3

Parents

Publications

22

Saving power by synthesizing gated clocks for sequential circuits

Luca Benini, Paul H. Siegel, Giovanni De Micheli · IEEE Design & Test of Computers · 1994 · 170 citations

, , +17

Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era

Kyeong‐Sik Min, Hiroshi Kawaguchi, T. Sakurai · 2003 · 99 citations

, , +17

A Power and Energy Exploration of Network-on-Chip Architectures

Arnab Banerjee, Robert Mullins, Simon W. Moore · 2007 · 92 citations

, , +17

Finite state machine decomposition for low power

José Monteiro, Arlindo L. Oliveira · 1998 · 87 citations · Full text

, , +17

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

Shmuel Wimer, Israel Koren · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013 · 62 citations

, , +17

1–5 of 22

Authors

95

  1. ZH
    Zhengfeng Huang

    Hefei University of Technology, China

    2 publications · 69 citations

    2

    h-index

  2. JC
    Jie Cui

    Anhui University, China

    2 publications · 69 citations

    2

    h-index

  3. MY
    Maoxiang Yi

    Hefei University of Technology, China

    2 publications · 69 citations

    2

    h-index

  4. AY
    Aibin Yan

    Anhui University, China

    2 publications · 69 citations

    2

    h-index

  5. TN
    Takafumi Nishikawa

    Nagasaki University, Japan

    1 publications · 10 citations

    1

    h-index

1–5 of 95

Institutions

41

  1. Hefei University of Technology

    Hefei, China

    2 h-index

    6 publications

    207 citations

  2. Anhui University

    Hefei, China

    2 h-index

    5 publications

    194 citations

  3. Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento

    Lisbon, Portugal

    1 h-index

    2 publications

    174 citations

  4. Amity University

    Noida, India

    1 h-index

    1 publications

    13 citations

  5. Centro Nacional de Microelectrónica

    Barcelona, Spain

    1 h-index

    3 publications

    57 citations

  6. Institut polytechnique de Grenoble

    Grenoble, France

    1 h-index

    4 publications

    96 citations

  7. Laboratoire d'Électronique des Technologies de l'Information

    Grenoble, France

    1 h-index

    4 publications

    96 citations

  8. Université Grenoble Alpes

    Saint-Martin-d'Hères, France

    1 h-index

    4 publications

    96 citations

1–8 of 41

Venues

  1. 2

    h-index

  2. IEEE Design & Test of Computers

    1 publications · 170 citations

    1

    h-index

  3. 1

    h-index

  4. 1

    h-index

1–4